1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More particularly, this invention relates to a flash EEPROM (Electrical Erasable and Programmable Read Only Memory) with improved read characteristics for data having multi values.
2. Description of the Related Art
Considerable attention has recently been given to non-volatile semiconductor memories, such as a ferro-electric memory, EPROM (Erasable and Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory). To store data, an EPROM and EEPROM use a floating gate for storing charges and a control gate for detecting a change in threshold voltage according to the presence or absence of charges in the floating gate. EEPROMs include a flash EEPROM which can perform data erasure for the entire memory chip or partial data erasure for each of a plurality of blocks in the memory cell array. There are two general types of memory cells in a flash EEPROM: a split gate type and a stacked gate type.
1) Split Gate Memory Cell
International Publication WO92/18980 discloses a split gate flash EEPROM. FIG. 1 presents a schematic cross-sectional view illustrating a split gate memory cell 101 disclosed in this publication.
The split gate memory cell 101, which is formed on a single crystalline silicon substrate 102 having a P type conductivity, has a source S of an N type conductivity, a drain D of the N type conductivity, and a channel CH defined between the source S and drain D. The memory cell 101 further has a first insulator film 103, a floating gate FG provided on the first insulator film 103, a second insulator film 104 provided on the floating gate FG, and a control gate CG provided on the second insulator film 104. A part of the control gate CG is arranged on the channel CH via the first insulator film 103 to serve as a select gate 105.
FIG. 2 is a block diagram showing a flash EEPROM 121 having a plurality of split gate memory cells 101. The flash EEPROM 121 includes a memory cell array 122, a row decoder 123, a column decoder 124, an address pad 125, an address buffer 126, an address latch 127, a data pin 128, an input buffer 129, a group of sense amplifiers 130, an output buffer 131, a source voltage controller 132, a drain voltage controller 133, a gate voltage controller 134 and a control core circuit 140.
The memory cell array 122 has a matrix of split gate memory cells 101, a plurality of word lines WLa to WLz, each commonly connected to the control gates CG of an associated row of memory cells 101, a plurality of bit lines BLa to BLz, each commonly connected to the drains D of an associated column of memory cells 101, and a common source line SL connected to the sources S of all the memory cells 101. The word lines WLa-WLz are connected to the row decoder 123, and the bit lines BLa-BLz are connected to the column decoder 124.
The address pad 125 receives a row address and a column address supplied from an external unit (not shown) and transfers the row and column addresses to the address latch 127 via the address buffer 126. The address latch 127 transfers the latched row address to the row decoder 123 and transfers the latched column address to the column decoder 124.
The row decoder 123 selects one word line (e.g., WLm) from the word lines WLa-WLz in accordance with the row address and connects the selected word line WLm to the gate voltage controller 134. The column decoder 124 selects one bit line (e.g., BLm) from the bit lines BLa-BLz in accordance with the column address and connects the selected bit line BLm to the sense amplifier groups 130 or the drain voltage controller 133.
The gate voltage controller 134 controls the electric potential on the word line WLm, which is connected thereto via the row decoder 123, in accordance with the individual operation modes shown in FIG. 3. The drain voltage control 133 controls the electric potential on the bit line BLm, which is connected thereto via the column decoder 124, in accordance with the individual operation modes shown in FIG. 3.
The common source line SL is connected to the source voltage controller 132, which controls the electric potential on the common source line SL in accordance with the individual operation modes shown in FIG. 3.
The data pin 128 receives data supplied from the external unit (not shown) and supplies the data to the input buffer 129. The input buffer 129 transfers the data to the column decoder 124. The column decoder 124 controls the electric potential on any selected one of the bit lines BLa-BLz in accordance with that data.
Data read from an arbitrary memory cell 101 is transferred from the associated one of the bit lines BLa-BLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes a plurality of sense amplifiers (not shown). The column decoder 124 operates to connect the selected bit line BLm to the sense amplifiers. The sense amplifier group 130 discriminates data and sends this data to the external unit via the output buffer 131 and the data pin 128.
The control core circuit 140 controls the operations of the row decoder 123, the column decoder 124, the address buffer 126, the address latch 127, the input buffer 129, the sense amplifier group 130, the output buffer 131, the source voltage controller 132, the drain voltage controller 133 and the gate voltage controller 134.
The individual operation modes (erase mode, write mode and read mode) of the flash EEPROM 121 will now be discussed referring to FIG. 3.
(a) Erase Mode
In erase mode, the electric potential on the common source line SL and all the bit lines BLa-BLz is held at the ground level (0 V). A voltage of 14 to 15 V is applied to a selected word line WLm, and the electric potentials on the non-selected word lines WLa-WLl and WLn-WLz are kept at the ground level. Therefore, the control gates CG of the individual memory cells 101 that are connected to the selected word line WLm are pulled up to 14 to 15 V. Accordingly, data stored in all the memory cells 101 connected to the selected word line WLm are erased.
When the electric potential of the control gate CG is 14 to 15 V and the electric potentials of the source and the substrate are 0 V, a high electric field is produced between the control gate CG and the floating gate FG. Then, a Fowler-Nordheim (FN) tunnel current flows between both gates. Consequently, electrons in the floating gate FG are pulled out to the control gate CG, so that data stored in the memory cells 101 are erased. This erasing operation is based on the electrostatic capacitances between the source S and the substrate 102 and floating gate FG being significantly greater than that between the control gate CG and the floating gate FG. Simultaneous selection of a plurality of word lines in the word lines WLa-WLz permits data erasure of all the memory cells 101 connected to the selected word lines. That is, as the memory cell array 122 is divided into a plurality of blocks corresponding to plural sets of word lines WLa-WLz, data erasure can be performed on each block. This erasing operation is called "block erasure".
(b) Write Mode
In write mode, the electric potential on the selected bit line BLm is kept at the ground level, while the electric potentials on the other bit lines (non-selected bit lines) BLa-BLl and BLn-BLz are kept at a level greater than the electric potential on the selected word line (in this case, 2 V).
A voltage of 2 V is applied to the word line WLm connected to the control gate CG of the selected memory cell 101, while the electric potentials on the other word lines (non-selected word lines) WLa-WLl and WLn-WLz are kept at the ground level. A voltage of 12 V is applied to the common source line SL.
Consequently, the electric potential of the floating gate FG is pulled up by the capacitive coupling between the source S and the floating gate FG. This produces a high electric field between the channel CH and the floating gate FG. Then, the electrons in the channel CH are accelerated to become hot electrons. Hot electrons are supplied to the floating gate FG as indicated by the arrow A in FIG. 1. As a result, charges are stored in the floating gate FG of the selected memory cell 101 and 1-bit data is written and stored there.
In each memory cell 101, a transistor, which includes a control gate CG, source S and drain D, has a threshold voltage Vth of 0.5 V. In the selected memory cell 101, therefore, electrons in the drain D are moved in the channel CH in the inverted state. Thus the current (cell current) flows to the drain D from the source S. This writing operation, unlike the erasing operation, may be executed for each selected memory cell 101.
(c) Read Mode
In read mode, a voltage of 4 V is applied to the word line WLm connected to the control gate CG of the selected memory cell 101, and the electric potentials on the other (non-selected) word lines WLa-WLl and WLn-WLz are held at the ground level. A voltage of 2 V is applied to the bit line BLm connected to the drain D of the selected memory cell 101, while the electric potentials on the other bit lines (non-selected bit lines) BLa-BLl and BLn-BLz are kept at the ground level.
As a result, the current (cell current), which flows to the source S of the memory cell 101 in the erased state from the drain D thereof, becomes greater than the cell current flowing in the memory cell 101 in the written state. This is because the channel CH directly below the floating gate FG of the data-erased memory cell 101 is enabled, while the channel CH directly below the floating gate FG of the data-written memory cell 101 is disabled. This will be discussed specifically.
As electrons are drained from the floating gate FG of the data-erased memory cell 101, the floating gate FG is positively charged. Therefore, the channel CH or the memory cell is enabled, permitting the current to flow. As electrons are supplied into the floating gate FG of the data-written memory cell 101, the floating gate FG is negatively charged. Thus, the channel CH or the memory cell is disabled to prevent the flow of the current.
Each sense amplifier in the sense amplifier group 130 discriminates the level of the cell current Id flowing in the associated memory cell 101 to read a data value stored in the memory cell 101. For instance, a data value "1" is read from the memory cell 101 in the erased state, and a data value "0" is read from the memory cell 101 in the written state. In this manner, binary data having a data value "1" indicating the erased state and a data value "0" indicating the written state are stored in each memory cell 101. Unlike the erasing operation, this reading operation may be performed for each selected memory cell 101.
U.S. Pat. No. 5,029,130 discloses a flash EEPROM in which the source S is called "drain" and the drain D is called "source". FIG. 4 is a schematic cross-sectional view illustrating a split gate memory cell 110, disclosed in this publication. FIG. 5 is a block diagram showing a flash EEPROM 111 that uses the split gate memory cells 110. FIG. 6 shows electric potentials on the individual lines and the substrate in the individual operation modes of the flash EEPROM 111.
The split gate memory cell 110 in FIG. 4 differs from the split gate memory cell 101 in that the source S and drain D in the former memory cell are called by the opposite names in the latter memory cell. Specifically, the source S in the memory cell 110 is called the drain D in the memory cell 101, while the drain D in the memory cell 110 is called the source S in the memory cell 101.
The flash EEPROM 111 in FIG. 5 differs from the flash EEPROM 121 in that the common source line SL is grounded. In any operation mode, the electron potential on the source line SL is kept at the ground level.
There has been a proposal to replace the source voltage controller 132 in the flash EEPROM 121 with a source current controller. In this case, the source current controller controls the electric potential on the common source line SL in accordance with the individual operation modes as shown in FIG. 3 by controlling the cell current value Id to a given value.
It has also been proposed to replace the drain voltage controller 133 in the flash EEPROM 121 or the flash EEPROM 111 with a drain current controller. In this case, the drain current controller controls the electric potential on the bit line BLm in accordance with the individual operation modes as shown in FIG. 3 or FIG. 6 by controlling the cell current value Id to a given value.
Further, it has been proposed to design the flash EEPROM 121 so as not to connect the sources S of the whole memory cells 110 to the common source line SL, but to selectively connect the sources S of a row of memory cells 110 to the common source line. In this case, the flash EEPROM 121 is provided with a source line decoder, which selects one source line in accordance with the column address and connects the selected source line to the source voltage controller 132.
In order to improve the integration of flash EEPROMs, recently, some attempts have been made to store data having three or more values (multi value) besides storing two-value (1-bit) data in each memory cell in the erased state and the written state.
FIG. 7 presents a characteristic graph illustrating the relationship between the value of the cell current Id flowing through the split gate memory cell 101 or 110 and the electric potential Vfg of the floating gate FG. This electric potential Vfg of the floating gate FG (hereinafter referred to as "floating gate potential") indicates the electric potential of the floating gate FG with respect to the electric potential of the source S and is closely associated with the cell current. As apparent from this graph, multi-value data having four values ("00", "01", "10" and "11"), for example, can be stored in each memory cell. The floating gate potential Vfg is given by the following equation: EQU Vfg=Vfgw+Vfgc
where Vfgw is the electric potential that is produced by the charges stored in the floating gate FG in write mode, and Vfgc is the potential produced by the capacitive coupling with the drain D. In a read operation, the electric potential Vfgc is constant so that the cell current value Id is primarily determined by the electric potential Vfgw. In a write operation, the amount of charges in the floating gate FG may be controlled by adjusting the write operation time or the applied voltage. That is, the floating gate potential Vfg may be controlled by adjusting the write operation time or the write operation voltage to control the amount of charges in the floating gate FG. This control permits the cell current value Id in read mode to be set to an arbitrary value.
Suppose that, as shown in FIG. 7, a data value "00" is associated with the area of the cell current value Id, which is less than 40 .mu.A, a data value "01" is associated with the area of the cell current value Id that is equal to or greater than 40 .mu.A and less than 80 .mu.A, a data value "10" is associated with the area of the cell current value Id that is equal to or greater than 80 .mu.A and less than 120 .mu.A, and a data value "11" is associated with the area of the cell current value Id that is equal to or greater than 120 .mu.A. In this case, the write operation time is adjusted such that individual floating gate potentials Vfg (Va, Vb and Vc) corresponding to the individual cell current values Id (40 .mu.A, 80 .mu.A and 120 .mu.A) in write mode are acquired.
Since electrons have been drained from the floating gate FG of a data-erased memory cell 101 or 110, that memory cell is in the same state as the state in which the data value "11" is stored. At this time, the floating gate has an electric potential Vfg equal to or greater than the electric potential Vc (2.5 V).
When the writing operation commences and charges are stored in the floating gate FG, the floating gate potential Vfg drops. If the writing operation is stopped when the floating gate potential Vfg becomes equal to or greater than Vb (1.5 V) and less than Vc (2.5 V), the data value "10" is written in the memory cell 101 or 110. If the writing operation is stopped at the time the floating gate potential Vfg becomes equal to or greater than Va (1.0 V) and less than Vb, the data value "01" is written in the memory cell 101 or 110. If the writing operation is stopped when the floating gate potential Vfg becomes less than Va, the data value "00" is written in the memory cell 101 or 110. In this manner, four-value (2-bit) data is stored in a single memory cell 101 or 111.
Since a constant voltage (4 V) is applied to the control gate CG in read mode, the channel CH serves as a constant resistor. Therefore, the transistor having the floating gate FG, the source S and the drain D are connected in series to the constant resistor (the channel CH) in the split gate memory cell 101 or 110. When the floating gate potential Vfg is less than a given value (3.5 V), therefore, the cell current value Id varies in accordance with the characteristics of the transistor.
When the floating gate potential Vfg is smaller than the threshold voltage Vth (0.5 V) of the transistor in the memory cell 101 or 110, which has the floating gate FG, the source S and the drain D, the cell current value Id is 0. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id increases (See FIG. 7). When the floating gate potential Vfg exceeds 3.5 V, the cell current value Id is saturated due to the dominance of the constant resistor (the channel CH).
2) Stacked Gate Memory Cell
FIG. 8 is a schematic cross-sectional view showing a stacked gate memory cell 201. The stacked gate memory cell 201 has a source S and a drain D both having an N type conductivity and defined on a single crystalline silicon substrate 202 having a P type conductivity, and a channel CH defined between the source S and the drain D. The stacked gate memory cell 201 further has a first insulator film 203, a floating gate FG arranged on the first insulator film 203, a second insulator film 204 arranged on the floating gate FG, and a control gate CG arranged on the second insulator film 204. The floating gate FG and the control gate CG are stacked one on the other without being deviating from each other. Therefore, the source S and the drain D are symmetrical to the gates FG and CG and the channel CH.
FIG. 9 is a block diagram showing a flash EEPROM 221 having a plurality of stacked gate memory cells 201. This flash EEPROM 221 differs from the flash EEPROM 121 using the split gate memory cells 101 shown in FIG. 1 in the following points:
(1) The memory cell array 122 has a plurality of stacked gate memory cells 201 arranged in a matrix form. PA1 (2) The sources S of the individual memory cells 201 aligned in individual columns are commonly connected to the associated bit lines BLa-BLz. PA1 (3) The drains D of all the memory cells 201 are connected to a common drain line DL, which is connected to a common drain line bias circuit 222. The bias circuit 222 controls the electric potential on the common drain line DL in accordance with the individual operation mode under the control of the control core circuit 140.
The names for the sources S and the drains D of the split gate memory cell 101 and the stacked gate memory cell 201 are determined based on the reading operation; the terminal to which a high electric potential is applied in the reading operation is called a "drain" while the terminal to which a low electric potential is applied is called a "source". The same applies to the names for those terminals, the source S or the drain D, in the writing operation and the erasing operation.
The individual operation modes (erase mode, write mode and read mode) of the flash EEPROM 221 will now be discussed referring to FIG. 10.
(a) Erase Mode
In erase mode, all the bit lines BLa-BLz are set in the open state and the electric potential on the selected word line WLm is kept at the ground level. The common drain line bias circuit 222 applies a voltage of 12 V to the drains D of the memory cells 201, connected to the selected word line WLm, via the common drain line DL. As a result, the FN tunnel current flows, and the electrons in the floating gates FG are drained toward the drains D, so that data stored in the memory cells 201 are erased. This erasing operation is executed for all the memory cells 201 connected to the selected word line WLm. By selecting a plurality of word lines in the word lines WLa-WLz, data in all the memory cells 201 connected to those selected word lines may be erased (block erasure).
(b) Write Mode
In write mode, a voltage of 12 V is applied to the word line WLm that is connected to the control gate CG of the selected memory cell 201, and the electric potentials on the other word lines (the non-selected word lines) WLa-WLl and WLn-WLz are kept at the ground level. A voltage of 5 V is applied to the bit line BLm connected to the source S of the selected memory cell 201, and the electric potentials on the other bit lines (the non-selected bit lines) BLa-BLl and BLn-BLz are kept at the ground level. The common drain line bias circuit 222 holds the electric potentials of the drains D of all the memory cells 201 at the ground level via the common drain line DL.
Then, the capacitive coupling with the control gates CG pulls up the electric potentials of the floating gates FG and causes hot electrons produced in the vicinity of the sources S to be supplied into the floating gates FG. As a result, charges are stored in the floating gate FG of the selected memory cell 201 and 1-bit data is written and stored there.
(c) Read Mode
In the read mode, a voltage of 5 V is applied to the word line WLm connected to the control gate CG of the selected memory cell 201, while the electric potentials on the other words lines (the non-selected word lines) WLa-WLl and WLn-WLz are held at the ground level. The electric potentials on all the bit lines BLa-BLz are kept at the ground level. The common drain line bias circuit 222 applies a voltage of 5 V to the drains D of all the memory cells 201 via the common drain line DL.
As a result, the cell current, which flows to the source S of any data-erased memory cell 201 from the drain D thereof, becomes greater than the cell current flowing in any data-written memory cell 201 as in the case of the split gate memory cell 101. It is thus possible to store two values, the data value "1" in the erased state and the data value "0" in the written state, in each memory cell 201.
A flash EEPROM using stacked gate memory cells 201 that store multi-value data has been proposed. FIG. 11 presents a characteristic graph illustrating the relationship between the value of the cell current Id flowing through the stacked gate memory cell 201 and the electric potential Vfg of the floating gate FG. The floating gate potential Vfg is the electric potential of the floating gate with respect to the electric potential of the source S.
In the stacked gate memory cell 201, the floating gate FG and the control gate CG are stacked on one another in alignment. In the stacked gate memory cell 201, unlike in the split gate memory cell 101, the channel CH does not serve as a constant resistor but has only the function of a transistor. When the floating gate potential Vfg is less than the threshold voltage Vth (1 V) of the memory cell 201, therefore, the cell current value Id become zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id is positively proportional to the floating gate potential Vfg, and multi-value data may be stored in the memory cell.
Even in the stacked gate memory cell 201, therefore, the floating gate potential Vfg is controlled by adjusting the write operation time or the applied voltage to control the amount of charges of the floating gate FG or the electric potential Vfg.
Suppose that, as shown in FIG. 11, the data value "00" is associated with the area of the cell current value Id which is less than 40 .mu.A, the data value "01" is associated with the area of the cell current value Id that is equal to or greater than 40 .mu.A and less than 80 .mu.A, the data value "10" is associated with the area of the cell current value Id that is equal to or greater than 80 .mu.A and less than 120 .mu.A, and the data value "11" is associated with the area of the cell current value Id that is equal to or greater than 120 .mu.A and less than 160 .mu.A. In this case, the write operation time is adjusted in such a way that individual floating gate potentials Vfg (Va, Vb, Vc and Vd) respectively correspond to the individual cell current values Id (40 .mu.A, 80 .mu.A, 120 .mu.A and 160 .mu.A). In this manner, four-value (2-bit) data may be stored in a single memory cell 201.
To accurately write data in the multi-value storing operation of a flash EEPROM, it is essential to precisely control the floating gate potential Vfg of the memory cell 101, 110 or 201 in write mode. That is, it is important to accurately set the floating gate potential Vfg of the memory cell after writing to the desired value. For example, Japanese Unexamined Patent Publication No. 4-57294 discloses a currently popular verify write technique.
The verify write technique first performs writing to memory cells 101, 110 or 201 for a given time (several hundred nanoseconds to several microseconds) and then performs a read operation for verification (verify read operation). In the subsequent writing operation, the data value to be written is compared with the data value that has been read in the read operation (comparing operation). The read data value is what has actually been written in the writing operation. When the data value to be written and the read data value do not match with each other, writing is executed again for a given time. The cycle of the writing operation, the verify read operation and the comparison is repeated until both data values match.
In the above-described non-volatile semiconductor memory, a data value that has been written is discriminated by comparing a read data value (the value of the current flowing in a memory cell) with a reference data value in the verify read operation.
The reference data value is generated by using a circuit that has a reference cell as shown in, for example, FIG. 12. FIG. 12 shows a circuit which is adapted for reading data from the memory cells 101 of the split gate flash EEPROM adapted for data writing and data reading. In general, the discrimination of 4-value data requires seven types of threshold values, namely, a threshold value E for verify read determination in erase mode, threshold values R1 to R3 for normal read determination, and threshold values P1 to P3 for verify read determination in write mode.
FIG. 13 shows the distribution of the cell current that an EEPROM for 4-value data requires. Although the cell current varies cell by cell, the cell current of each cell should fall within four ranges corresponding to four values. For this purpose, seven types of threshold values are set between the individual current ranges.
The circuit in FIG. 12 has seven reference cells 301 to 307 associated with the seven threshold values needed for reading and determining 4-value data and a reference cell switching circuit 308 for selectively connecting the reference cell necessary for each operation to a sense amplifier circuit 309.
The sense amplifier circuit 309 compares the reference current, which is produced in the selected reference cell, with the actual current that flows through the memory cell 101 of interest and outputs the comparison result. When the reference current is equal to or larger than the real current, for example, a signal of an H (High) level is output. When the reference current is less than the real current, a signal of an L (Low) level is output. This sense amplifier circuit 309 is incorporated in the sense amplifier group 130. In FIG. 12, the column decoder 124 located between the memory cells 101 and the sense amplifier circuit 309 is omitted for simplifying this description.
The circuit in FIG. 12 further comprises a reference potential generator 310 for applying voltages to the floating gates FG of the reference cells 301-307. This generator 310 is provided to easily acquire from the reference cells the currents used as references for the determination in read mode. The voltages generated by this generator 310 are not applied to the memory cells 101 or 110. Note that there is a case where a stacked gate flash EEPROM uses ordinary MOS transistors that do not have floating gates as reference cells.
To directly apply a voltage to the floating gate FG, the reference cells 301-307 in the prior art are formed with different shapes and in a different process from those of the actual memory cells 101. Even if the reference cells 301-307 are designed strictly, the formed reference cells would have characteristics little different from those of the actual memory cells due to a slight process variation. This variation in characteristics does not raise a significant problem in a binary memory, which affords a large margin for the threshold values for data determination. In a multi-value memory, which cannot afford a large margin for the threshold values for data determination, however, such a variation may raise a problem like an error in data discrimination based on the threshold values or the occurrence of an undiscriminatable state. This problem becomes more serious as the number of values in multi-value data increases.